1. Field of the Invention
The invention is directed to an interconnect structure formed in a low-k dielectric layer and a process for forming same.
2. Description of the Related Art
Damascene processes are well known for forming conductive interconnect structures in semiconductor devices. Both single- and dual-damascene processes include forming vias and trenches in a layer of dielectric material, e.g., an intermetal dielectric layer (IMD), and filling the vias and trenches with a conductive material such as aluminum or copper. More recently, as device dimensions have continued to decrease and via and trench widths have become correspondingly smaller, there has been an ongoing concern about increased signal propagation delay caused by the combined effect of the resistance and capacitance (RC delay) associated with the interconnect structures. In an attempt to reduce the RC delay, copper is often used as an interconnect material instead of aluminum because copper has a lower resistivity, and techniques have been developed to successfully deposit copper to form interconnect structures. In order to further improve RC delay, dielectric materials having a lower dielectric constant than conventional dielectric materials, sometimes referred to as low-k dielectric materials, have also been employed. In general, low-k dielectric materials are materials having a dielectric constant less than about 3.9, which is an approximate lower end of a range of dielectric constants for conventional dielectric materials such as silicon dioxide.
In both the single- and dual-damascene processes, several layers are formed on a substrate. Namely, a low-k dielectric layer is formed on an etch stop layer (ESL), and a cap layer is formed on the low-k dielectric layer. A photoresist layer is then deposited on the cap layer and patterned to define locations where vias and/or trenches are to be etched through the cap layer and the low-k dielectric layer. The photoresist layer is next removed after completion of such etching.
Sidewalls of the trench or via formed in the low-k dielectric layer, however, may be damaged during the etching and/or photoresist removal operations. Such damage to the low-k layer causes the dielectric constant of the low-k layer to increase to a level approaching that of a conventional dielectrical material such as silicon dioxide. As a result, RC delay is increased. Possible solutions proposed for addressing this problem have included performing additional processing steps to repair the damaged portions of the low-k dielectric layer in order to restore the desired low dielectric constant. Such solutions have only achieved limited success.